1. Technical Field
The present invention relates to the design of integrated circuits and more specifically optimizing a buffer tree in an integrated circuit.
2. Description of the Related Art
During the development of an integrated circuit, electronic design automation (EDA) tools place source components and sink components at various locations during physical layout steps. As one skilled in the art can appreciate, “components” may be logic gates (AND, OR, NAND, etc.), latches, or other entities that provide or receive electrical signals, such as for data or clock information. A “source” is a component that delivers or drives a signal, and a “sink” is a component that receives or loads the signal. Many of the EDA tools available create buffer trees (e.g., drivers), which propagate the signals from source components to distant sink components, in a less than optimal manner due to a wide variety of sink component configurations and fanout considerations relative to the source component. As one skilled in the art can appreciate, a “buffer” receives an electrical signal from one component and retransmits the electrical signal to another component (or subsequent buffer). This can cause timing issues in the device's design due to the fact that each buffer introduces a delay between a source component and a sink component.